Addressing Modes in 8085
There are five addressing modes in 8085.
1. Immediate Addressing Mode: - An immediate is transferred directly to the register.
Eg: - MVI A, 30H (30H is copied into the register A)
RLC, RRC, RAL, RAR, CMA, CMC, STC
1. RLC: - Each binary bit of the accumulator is rotated left by one position. Bit D7 is placed in the position of D0 as well as in the Carry flag. CY is modified according to bit D7. Any other bit is not affected.
CMP, CPI, ANA, ANI, XRA,XRI, ORA, ORI
1. CMP: - (compare register or memory with accumulator) The contents of the operand register or memory are M compared with the contents of the accumulator. Both contents are preserved . The result of the comparison is shown by setting the flags of the PSW as follows:
if (A) < reg/mem: carry flag is set.
if (A) = reg/mem:
if (A) = reg/mem:
XCHG, SPHL, XHTL, PUSH, POP, OUT, IN
10. XCHG: - Exchange H and L with D and E. The contents of register H are exchanged with the contents of register D, and the contents of register L are exchanged with the contents of register E.
Eg: - XCHG
11. SPHL: - This instruction copies H and L register to the stack pointer. The instruction loads
MOV, MVI, LDA, LDAX, LXI, LHLD, STA, STAX,SHLD
1.MOV: - This instruction is used to copy the data from one place to another.
Eg: - MOV Rd, Rs (This instruction copies the content of Rs to Rd)
MOV M,Rs (This instruction copies the content of register Rs to memory location pointed by HL Register)
MOV Rd, M (This instruction copies the content of memory location pointed by the HL
NOP, HLT, DI, EI, RIM, SIM
1.NOP(No operation): - No operation is performed. The instruction is fetched and decoded. However no operation is executed.
Eg: - NOP
2. HLT(Halt): - The CPU finishes executing the current instruction and halts any further
PCHL, RST
1. PCHL: - Load program counter with HL contents. The contents of registers H and L are copied into the program counter. The contents of H are placed as the high-order byte and the contents of L as the low order byte.
2. RST: - The RST instruction is equivalent to a 1- byte call instruction to one of eight memory
Return Instruction, RC, RNC, RP, RM, RZ, RNZ,RPE, RPO, RET
The program sequence is transferred from the subroutine to the calling program based on the specified flag of the PSW as described below. The two bytes from the top of the stack are copied into the program counter, and program execution begins at the new address.
1. RC: - (conditional call) The program sequence is transferred to a particular level or a 16-bit address if C=1 (or carry is 1)
Eg: - RC ABC (jump to the level abc if C=1)
2. RNC: - (conditional call) The program sequence is transferred to a particular level or a 16-bit
Call Instruction, CC, CNC, CP, CM, CZ, CNZ, CPE, CPO
1. CC: - (conditional call) The program sequence is transferred to a particular level or a 16-bit address if C=1 (or carry is 1)
Eg: - CC ABC (jump to the level abc if C=1)
2. CNC: - (conditional call) The program sequence is transferred to a particular level or a 16-bit address if C=0 (or carry is 0)
Eg: - CNC ABC (jump to the level abc if C=0)
3. CP: - (conditional call) The program sequence is transferred to a particular level or a 16-bit
Jump Instruction, JMP, JC, JNC, JP, JM, JZ, JNZ, JPE, JPO
1. JMP: - (unconditionally jump) The program sequence is transferred to the memory location specified by the16-bit address given in the operand.
Eg: - JMP 2034H ( jump to location 2034H) there is no condition to jump.
JMP ABC (jump to abc level)
2. JC: - (conditional jump) The program sequence is transferred to a particular level or a 16-bit address if C=1 (or carry is 1)
INR, INX, DCR, DCX, DAA instruction
11. INR: - The contents of the designated register or memory) are incremented by 1 and the result is stored in the same place. If the operand is a memory location, its location is specified by the contents of the HL registers.
Eg: -INR B( the content of register B is incremented by 1.
INR M( the content of memory location pointed by HL pair in incremented by 1)
12. INX: - Increment register pair by 1.
Eg: INX H (It means the location pointed by the HL pair is incremented by 1)
13.DCR: - The contents of the designated register or memory are M decremented by 1 and the
SUB, SBB, SUI, SBI, instruction
7. SUB: - substract the content of a register or a memory location form the content of accumulator and the result is stored in the accumulator.
Eg: - SUB B( it substracts the content of B register from the content of the accumulator.
SUB M( it substracts the content of memory location pointed by HL pair from the content of
Eg: - SUB B( it substracts the content of B register from the content of the accumulator.
SUB M( it substracts the content of memory location pointed by HL pair from the content of
LXI, DAD, instruction
5. LXI: Load register Pair immediate
Eg:- LXI H, 2030H (This instruction loads the memory address in HL register, here it works as memory pointer)
Arithmetic Instruction In 8085, ADD, ADC, ADI, ACI
There are some of the important instructions in 8085 microprocessor.
1. ADD: - The content of operand are added to the content of the accumulator and the result is stored in Accumulator.
Eg- ADD B (it adds the content of accumulator to the content of the register B)
ADD M (if content is stored in memory location the it is added with the content stored in accumulator)
2. ADC: -
Flag Registers In 8086, Conditional flag,
The Conditional Flag:-
There are six conditional flag.
- The Parity Flag(PF)
- The Zero Flag(ZF)
- The Sign Flag(SF)
Flag Registers In 8086
Flag Register:-
It is a 16-bit register with each bit corresponding to a flip-flop. It changes its status according to the stored output in the accumulator. A flag can control certain operation of the EU.
The Execution Unit, EU
The execution unit(EU):
The main function of EU is decoding and execution of the instructions. It tells the BIU that where to fetch instructions or data from.
Different Parts of Execution Unit(EU):-
Bus Interface Unit, BIU, __Continue........
Instruction Pointer:-
• It is 16-bit register, which identifies the location of the next word of instruction code that is to be fetched in the current code segment.
• IP contains an offset instead of the actual address of the next instruction.
• The 20-bit address produced after addition of the offset stored in IP to segment base address in the CS is called the Physical address of the code byte.
Bus Interface Unit, BIU
The Bus Interface unit (BIU)
This unit handles all transfer of data and addresses on the buses for the EU(execution unit). This unit sends out addresses, fetches instructions from memory, reads data from ports and memory and writes data to ports and memory.
Different Parts of BIU:
a.Segment Register
